This specification relates to polishing pads useful for polishing and planarizing substrates and particularly to polishing pads having uniform polishing properties.
Polyurethane polishing pads are the primary pad-type for a variety of demanding precision polishing applications. These polyurethane polishing pads are effective for polishing silicon wafers, patterned wafers, flat panel displays and magnetic storage disks. In particular, polyurethane polishing pads provide the mechanical integrity and chemical resistance for most polishing operations used to fabricate integrated circuits. For example, polyurethane polishing pads have high strength for resisting tearing; abrasion resistance for avoiding wear problems during polishing; and stability for resisting attack by strong acidic and strong caustic polishing solutions.
The production of semiconductors typically involves several chemical mechanical planarization (CMP) processes. In each CMP process, a polishing pad in combination with a polishing solution, such as an abrasive-containing polishing slurry or an abrasive-free reactive liquid, removes excess material in a manner that planarizes or maintains flatness for receipt of a subsequent layer. The stacking of these layers combines in a manner that forms an integrated circuit. The fabrication of these semiconductor devices continues to become more complex due to requirements for devices with higher operating speeds, lower leakage currents and reduced power consumption. In terms of device architecture, this translates to finer feature geometries and increased metallization levels. These increasingly stringent device design requirements are driving the adoption of copper metallization in conjunction with new dielectric materials having lower dielectric constants. The diminished physical properties, frequently associated with low k and ultra-low k materials, in combination with the devices' increased complexity have led to greater demands on CMP consumables, such as polishing pads and polishing solutions.
In particular, low k and ultra-low k dielectrics tend to have lower mechanical strength and poorer adhesion in comparison to conventional dielectrics, rendering planarization more difficult. In addition, as integrated circuits' feature sizes decrease, CMP-induced defectivity, such as, scratching becomes a greater issue. Furthermore, integrated circuits' decreasing film thickness requires improvements in defectivity while simultaneously providing acceptable topography to a wafer substrate—these topography requirements demand increasingly stringent planarity, dishing and erosion specifications.
Casting polyurethane into cakes and cutting the cakes into several thin polishing pads has proven to be an effective method for manufacturing polishing pads with consistent reproducible polishing properties. Vishwanathan et al., in PCT Pub. No. 01.91971 disclose a set of properties for improving polishing performance including E′ (elastic storage modulus) ratio at 30° C. and 90° C. and several other properties. Unfortunately, polyurethane pads produced from the casting and skiving method can have polishing variations arising from a polishing pad's casting location. For example, pads cut from a bottom casting location and a top casting can have different densities and porosities. Furthermore, polishing pads can have center-to-edge variations in density and porosity within a pad. These variations can adversely affect polishing for the most demanding applications, such as low k patterned wafers. Thus, there is a demand for a polyurethane polishing pad with improved density and porosity uniformity.